commit 519807f7beec071583e5c869ac2666dac2e50542
author Diana Picus <diana.picus@linaro.org> Mon Dec 19 11:26:31 2016 +0000
committer Diana Picus <diana.picus@linaro.org> Mon Dec 19 11:26:31 2016 +0000
tree f2aeddc1cf608fd78304498b303a038f1e295503
parent b29a15ecad3f1374827820db66bd872dae89ee0e

[ARM] GlobalISel: Support loading from the stack

Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

llvm-svn: 290096

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 53298f6..c01043d 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -75,11 +75,27 @@
     return true;
   }
 
-  if (I.getOpcode() == TargetOpcode::G_ADD) {
+  MachineInstrBuilder MIB{MF, I};
+
+  using namespace TargetOpcode;
+  switch (I.getOpcode()) {
+  case G_ADD:
     I.setDesc(TII.get(ARM::ADDrr));
-    AddDefaultCC(AddDefaultPred(MachineInstrBuilder(MF, I)));
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+    AddDefaultCC(AddDefaultPred(MIB));
+    break;
+  case G_FRAME_INDEX:
+    // Add 0 to the given frame index and hope it will eventually be folded into
+    // the user(s).
+    I.setDesc(TII.get(ARM::ADDri));
+    AddDefaultCC(AddDefaultPred(MIB.addImm(0)));
+    break;
+  case G_LOAD:
+    I.setDesc(TII.get(ARM::LDRi12));
+    AddDefaultPred(MIB.addImm(0));
+    break;
+  default:
+    return false;
   }
 
-  return false;
+  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }

llvm/lib/Target/ARM/ARMLegalizerInfo.cpp

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 6567950..6680196 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -25,8 +25,14 @@
 
 ARMLegalizerInfo::ARMLegalizerInfo() {
   using namespace TargetOpcode;
+  const LLT p0 = LLT::pointer(0, 32);
   const LLT s32 = LLT::scalar(32);
 
+  setAction({G_FRAME_INDEX, p0}, Legal);
+
+  setAction({G_LOAD, s32}, Legal);
+  setAction({G_LOAD, 1, p0}, Legal);
+
   setAction({G_ADD, s32}, Legal);
 
   computeTables();

llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp

diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 02100aa..9bd036a 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -103,12 +103,25 @@
       return Mapping;
   }
 
-  if (Opc == TargetOpcode::G_ADD) {
-    unsigned NumOperands = MI.getNumOperands();
-    ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
-    return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
-                              NumOperands};
+  using namespace TargetOpcode;
+
+  unsigned NumOperands = MI.getNumOperands();
+  const ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
+
+  switch (Opc) {
+  case G_ADD:
+  case G_LOAD:
+    // FIXME: We're abusing the fact that everything lives in a GPR for now; in
+    // the real world we would use different mappings.
+    OperandsMapping = &ARM::ValueMappings[0];
+    break;
+  case G_FRAME_INDEX:
+    OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
+    break;
+  default:
+    return InstructionMapping{};
   }
 
-  return InstructionMapping{};
+  return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
+                            NumOperands};
 }