| commit | 51ed131ed2e745a850f4283a96d25a48d6ee2f44 | [log] [tgz] |
|---|---|---|
| author | Derek Schuff <dschuff@google.com> | Tue Aug 07 21:24:01 2018 +0000 |
| committer | Derek Schuff <dschuff@google.com> | Tue Aug 07 21:24:01 2018 +0000 |
| tree | ccbfeb4ac5566acf445a264b2d3584b38c4d81dd | |
| parent | dca675a0d8f4cbbaf2530b6b7e0bdda1b4a83600 [diff] [blame] |
[WebAssembly] Update SIMD binary arithmetic Add missing SIMD types (v2f64) and binary ops. Also adds tablegen support for automatically prepending prefix byte to SIMD opcodes. Differential Revision: https://reviews.llvm.org/D50292 Patch by Thomas Lively llvm-svn: 339186
diff --git a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp index d5763d8..c040c81 100644 --- a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
@@ -229,7 +229,9 @@ case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: + case MVT::v2i64: case MVT::v4f32: + case MVT::v2f64: return "v128"; case MVT::ExceptRef: return "except_ref";