commit | 522fb7eedc1bc6257a5aad9938ca0c47b5ad07e5 | [log] [tgz] |
---|---|---|
author | Tim Northover <tnorthover@apple.com> | Fri Aug 02 14:09:49 2019 +0000 |
committer | Tim Northover <tnorthover@apple.com> | Fri Aug 02 14:09:49 2019 +0000 |
tree | d7ab329fb45fb33459eaa0e1500ed679b9f56375 | |
parent | deb61871d3020cee93e6f9a3badc91a09c319fd5 [diff] [blame] |
GlobalISel: support swiftself attribute llvm-svn: 367683
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index 849f955..9b8a12e 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -106,6 +106,7 @@ Register ArgsReg, const EVT &VT) override; virtual void markPhysRegUsed(unsigned PhysReg) { + MIRBuilder.getMRI()->addLiveIn(PhysReg); MIRBuilder.getMBB().addLiveIn(PhysReg); }