commit 52a956da5242544260b8063d9b1d5a35a6308a66
author Chris Lattner <sabre@nondot.org> Tue Jun 20 23:18:58 2006 +0000
committer Chris Lattner <sabre@nondot.org> Tue Jun 20 23:18:58 2006 +0000
tree 77139083c6fc2378b1f63308159c17032a0b8df5
parent 5705d4d519862795a8261bf38367c6b2a1930ac5

Rename OR4 -> OR.  Move some PPC64-specific stuff to the 64-bit file

llvm-svn: 28889

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 9390442..a2ba4fe 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -35,7 +35,7 @@
                                unsigned& sourceReg,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR ||
+  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&