ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
llvm-svn: 184964
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 647fdb3..f80fba6 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4966,12 +4966,12 @@
} else
CanAcceptCarrySet = false;
- if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
- Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
- Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
- Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
- Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
- (Mnemonic == "clrex" && !isThumb()) ||
+ if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "cps" ||
+ Mnemonic == "mcr2" || Mnemonic == "it" || Mnemonic == "mcrr2" ||
+ Mnemonic == "cbz" || Mnemonic == "cdp2" || Mnemonic == "trap" ||
+ Mnemonic == "mrc2" || Mnemonic == "mrrc2" || Mnemonic == "setend" ||
+ ((Mnemonic == "clrex" || Mnemonic == "dmb" || Mnemonic == "dsb" ||
+ Mnemonic == "isb") && !isThumb()) ||
(Mnemonic == "nop" && isThumbOne()) ||
((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||