update testcases for x86 fastcc changes.
llvm-svn: 26842
diff --git a/llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll b/llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll
index 43f6493..c9f9cee 100644
--- a/llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll
+++ b/llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -1,7 +1,9 @@
; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov %EDX, 1'
-
; check that fastcc is passing stuff in regs.
+; Argument reg passing is disabled due to regalloc issues. FIXME!
+; XFAIL: *
+
declare fastcc long %callee(long)
long %caller() {