Added RFE for disassembly only.
B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.
llvm-svn: 96519
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 5b06bea..d1793d0 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -957,7 +957,7 @@
[/* For disassembly only; pattern left blank */]>;
}
-// Store Return State -- for disassembly only
+// Store Return State is a system instruction -- for disassembly only
def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
NoItinerary, "srs${addr:submode}\tsp!, $mode",
[/* For disassembly only; pattern left blank */]> {
@@ -972,6 +972,21 @@
let Inst{22-20} = 0b100; // W = 0
}
+// Return From Exception is a system instruction -- for disassembly only
+def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
+ NoItinerary, "rfe${addr:submode}\t$base!",
+ [/* For disassembly only; pattern left blank */]> {
+ let Inst{31-28} = 0b1111;
+ let Inst{22-20} = 0b011; // W = 1
+}
+
+def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
+ NoItinerary, "rfe${addr:submode}\t$base",
+ [/* For disassembly only; pattern left blank */]> {
+ let Inst{31-28} = 0b1111;
+ let Inst{22-20} = 0b001; // W = 0
+}
+
//===----------------------------------------------------------------------===//
// Load / store Instructions.
//