MIR Serialization: Serialize simple MachineRegisterInfo attributes.
This commit serializes the 3 scalar boolean attributes from the
MachineRegisterInfo class: IsSSA, TracksRegLiveness, and
TracksSubRegLiveness. These attributes are serialized as part
of the machine function YAML mapping.
Reviewers: Duncan P. N. Exon Smith
Differential Revision: http://reviews.llvm.org/D10618
llvm-svn: 240579
diff --git a/llvm/test/CodeGen/MIR/machine-function.mir b/llvm/test/CodeGen/MIR/machine-function.mir
index a3c1d1d..8f053ad 100644
--- a/llvm/test/CodeGen/MIR/machine-function.mir
+++ b/llvm/test/CodeGen/MIR/machine-function.mir
@@ -25,7 +25,7 @@
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: foo
...
---
@@ -33,7 +33,7 @@
# CHECK-NEXT: alignment:
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: bar
...
---
@@ -41,7 +41,7 @@
# CHECK-NEXT: alignment: 8
# CHECK-NEXT: exposesReturnsTwice: false
# CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
name: func
alignment: 8
...
@@ -50,7 +50,7 @@
# CHECK-NEXT: alignment: 16
# CHECK-NEXT: exposesReturnsTwice: true
# CHECK-NEXT: hasInlineAsm: true
-# CHECK-NEXT: ...
+# CHECK: ...
name: func2
alignment: 16
exposesReturnsTwice: true
diff --git a/llvm/test/CodeGen/MIR/register-info.mir b/llvm/test/CodeGen/MIR/register-info.mir
new file mode 100644
index 0000000..c01997b
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/register-info.mir
@@ -0,0 +1,36 @@
+# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses machine register info properties
+# correctly.
+
+--- |
+
+ define i32 @foo() {
+ entry:
+ ret i32 0
+ }
+
+ define i32 @bar() {
+ start:
+ ret i32 0
+ }
+
+...
+---
+# CHECK: name: foo
+# CHECK: isSSA: false
+# CHECK-NEXT: tracksRegLiveness: false
+# CHECK-NEXT: tracksSubRegLiveness: false
+# CHECK: ...
+name: foo
+...
+---
+# CHECK: name: bar
+# CHECK: isSSA: false
+# CHECK-NEXT: tracksRegLiveness: true
+# CHECK-NEXT: tracksSubRegLiveness: true
+# CHECK: ...
+name: bar
+isSSA: false
+tracksRegLiveness: true
+tracksSubRegLiveness: true
+...