Reordered registers slightly to simplify a new check.
Added a function to map between the caller's and callee's register windows.
llvm-svn: 941
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
index ff04e3f..311d035 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
@@ -23,8 +23,9 @@
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"i0", "i1", "i2", "i3", "i4", "i5",
+ "i6", "i7",
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "i6", "i7", "o6" };
+ "o6" };
@@ -56,8 +57,8 @@
// --- following colors are not available for allocation within this phase
// --- but can appear for pre-colored ranges
- g0, g1, g2, g3, g4, g5, g6, g7, i6, i7, o6
-
+ i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
+
//*** NOTE: If we decide to use globals, some of them are volatile
//**** see sparc64ABI (change isRegVloatile method below)
@@ -77,6 +78,16 @@
return IntRegNames[reg];
}
+ static unsigned int getRegNumInCallersWindow(const unsigned reg) {
+ if (reg <= l7 || reg == o6) {
+ assert(0 && "registers o0-o7 and l0-l7 are not visible in caller");
+ return reg;
+ }
+ if (reg <= i7)
+ return reg - (i0 - o0);
+ assert((reg >= g0 || reg <= g7) && "Unrecognized integer register number");
+ return reg;
+ }
};