Fix an assertion in DwarfExpression when emitting fragments in vector registers
When DwarfExpression is emitting a fragment that is located in a
register and that fragment is smaller than the register, and the
register must be composed from sub-registers (are you still with me?)
the last DW_OP_piece operation must not be larger than the size of the
fragment itself, since the last piece of the fragment could be smaller
than the last subregister that is being emitted.
rdar://problem/29779065
llvm-svn: 290324
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
index 5419a10..61b2c7e 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -86,7 +86,7 @@
}
bool DwarfExpression::AddMachineReg(const TargetRegisterInfo &TRI,
- unsigned MachineReg) {
+ unsigned MachineReg, unsigned MaxSize) {
if (!TRI.isPhysicalRegister(MachineReg))
return false;
@@ -137,10 +137,12 @@
// its range, emit a DWARF piece for it.
if (Reg >= 0 && Intersection.any()) {
AddReg(Reg, "sub-register");
+ if (Offset >= MaxSize)
+ break;
// Emit a piece for the any gap in the coverage.
if (Offset > CurPos)
AddOpPiece(Offset - CurPos);
- AddOpPiece(Size);
+ AddOpPiece(std::min<unsigned>(Size, MaxSize - Offset));
CurPos = Offset + Size;
// Mark it as emitted.
@@ -196,9 +198,12 @@
bool ValidReg = false;
auto Op = ExprCursor.peek();
switch (Op->getOp()) {
- default:
- ValidReg = AddMachineReg(TRI, MachineReg);
+ default: {
+ auto Fragment = ExprCursor.getFragmentInfo();
+ ValidReg = AddMachineReg(TRI, MachineReg,
+ Fragment ? Fragment->SizeInBits : ~1U);
break;
+ }
case dwarf::DW_OP_plus:
case dwarf::DW_OP_minus: {
// [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].