GlobalISel: select small binary operations on AArch64.
AArch64 actually supports many 8-bit operations under the definition used by
GlobalISel: the designated information-carrying bits of a GPR32 get the right
value if you just use the normal 32-bit instruction.
llvm-svn: 284526
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index ebfd78b..eb2614d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -123,8 +123,13 @@
unsigned OpSize) {
switch (RegBankID) {
case AArch64::GPRRegBankID:
- switch (OpSize) {
- case 32:
+ if (OpSize <= 32) {
+ assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV &&
+ GenericOpc != TargetOpcode::G_UDIV &&
+ GenericOpc != TargetOpcode::G_LSHR &&
+ GenericOpc != TargetOpcode::G_ASHR)) &&
+ "operation should have been legalized before now");
+
switch (GenericOpc) {
case TargetOpcode::G_OR:
return AArch64::ORRWrr;
@@ -149,7 +154,7 @@
default:
return GenericOpc;
}
- case 64:
+ } else if (OpSize == 64) {
switch (GenericOpc) {
case TargetOpcode::G_OR:
return AArch64::ORRXrr;
@@ -676,7 +681,7 @@
unsigned ZeroReg;
unsigned NewOpc;
- if (Ty == LLT::scalar(32)) {
+ if (Ty.isScalar() && Ty.getSizeInBits() <= 32) {
NewOpc = AArch64::MADDWrrr;
ZeroReg = AArch64::WZR;
} else if (Ty == LLT::scalar(64)) {