AMDGPU: Fix name for v_ashrrev_i16
llvm-svn: 289967
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 37e31f57..64e2bf2 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -340,7 +340,7 @@
def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
-defm V_ASHRREV_B16 : VOP2Inst <"v_ashrrev_b16", VOP_I16_I16_I16>;
+defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
let isCommutable = 1 in {
@@ -443,7 +443,7 @@
defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
-defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_B16_e32>;
+defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e32>;
def : ZExt_i16_i1_Pat<zext>;
def : ZExt_i16_i1_Pat<anyext>;
@@ -689,7 +689,7 @@
defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
-defm V_ASHRREV_B16 : VOP2_Real_e32e64_vi <0x2c>;
+defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;