[RISCV] Add inline asm constraints I, J & K for RISC-V
This allows the constraints I, J & K to be used in inline asm for
RISC-V, with the following semantics (equivalent to GCC):
I: Any 12-bit signed immediate.
J: Integer zero only.
K: Any 5-bit unsigned immediate.
See the GCC definitions here:
https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
Differential Revision: https://reviews.llvm.org/D54091
llvm-svn: 363055
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 1eb36d1..f800bb0 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
return llvm::makeArrayRef(GCCRegAliases);
}
+bool RISCVTargetInfo::validateAsmConstraint(
+ const char *&Name, TargetInfo::ConstraintInfo &Info) const {
+ switch (*Name) {
+ default:
+ return false;
+ case 'I':
+ // A 12-bit signed immediate.
+ Info.setRequiresImmediate(-2048, 2047);
+ return true;
+ case 'J':
+ // Integer zero.
+ Info.setRequiresImmediate(0);
+ return true;
+ case 'K':
+ // A 5-bit unsigned immediate for CSR access instructions.
+ Info.setRequiresImmediate(0, 31);
+ return true;
+ }
+}
+
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
Builder.defineMacro("__ELF__");