commit 56d4022997945fc1ea56bb7c439042294d5529db
author Craig Topper <craig.topper@gmail.com> Wed Feb 22 06:54:18 2017 +0000
committer Craig Topper <craig.topper@gmail.com> Wed Feb 22 06:54:18 2017 +0000
tree e9076735365f9d339e586b7104f7228ad1d9c900
parent 5cd6c5cacff5f2ec87724b7c4079b493bbbe097f

[AVX-512] Allow legacy scalar min/max intrinsics to select EVEX instructions when available

This patch introduces new X86ISD::FMAXS and X86ISD::FMINS opcodes. The legacy intrinsics now lower to this node. As do the AVX-512 masked intrinsics when the rounding mode is CUR_DIRECTION.

I've merged a copy of the tablegen multiclass avx512_fp_scalar into avx512_fp_scalar_sae. avx512_fp_scalar still needs to support CUR_DIRECTION appearing as a rounding mode for X86ISD::FADD_ROUND and others.

Differential revision: https://reviews.llvm.org/D30186

llvm-svn: 295810

llvm/lib/Target/X86/X86InstrFormats.td

diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index 824e4df..c2fe786 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -455,7 +455,7 @@
          Domain d = GenericDomain>
       : I<o, F, outs, ins, asm, pattern, itin, d> {
   let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512],
-                   !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX],
+                   !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX],
                    !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1],
                    !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
                    !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2],