[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.
If -simplify-mir option is passed then MIRPrinter will not print such fields.
This change also required some lit test cases in CodeGen directory to be changed.
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D32304
llvm-svn: 304779
diff --git a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
index 883f6fd..6920611 100644
--- a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
@@ -50,12 +50,12 @@
adjustsStack: true
hasCalls: true
# CHECK: fixedStack:
-# CHECK-NEXT: , callee-saved-register: '%rbx' }
+# CHECK: , callee-saved-register: '%rbx' }
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
# CHECK: stack:
# CHECK-NEXT: - { id: 0
-# CHECK-NEXT: , callee-saved-register: '%edi' }
+# CHECK: callee-saved-register: '%edi'
stack:
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
index a7ecac8..c87cb0b 100644
--- a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
@@ -20,7 +20,7 @@
stackSize: 4
maxAlignment: 4
# CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, isImmutable: true,
fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
stack:
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index b9e47cd..78951de 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -19,11 +19,11 @@
---
name: test_vregs
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _ }
-# CHECK-NEXT: - { id: 1, class: _ }
-# CHECK-NEXT: - { id: 2, class: _ }
-# CHECK-NEXT: - { id: 3, class: _ }
-# CHECK-NEXT: - { id: 4, class: _ }
+# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
index 63019da..abdcda2 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
+# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
# Test various aspects of register class specification on machine operands.
--- |
define void @func() { ret void }
@@ -6,11 +6,11 @@
---
# CHECK-LABEL: name: func
# CHECK: registers:
-# CHECK: - { id: 0, class: gr32 }
-# CHECK: - { id: 1, class: gr64 }
-# CHECK: - { id: 2, class: gr32 }
-# CHECK: - { id: 3, class: gr16 }
-# CHECK: - { id: 4, class: _ }
+# CHECK: - { id: 0, class: gr32, preferred-register: '' }
+# CHECK: - { id: 1, class: gr64, preferred-register: '' }
+# CHECK: - { id: 2, class: gr32, preferred-register: '' }
+# CHECK: - { id: 3, class: gr16, preferred-register: '' }
+# CHECK: - { id: 4, class: _, preferred-register: '' }
name: func
body: |
bb.0:
diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
index 27ca266..310fa6a 100644
--- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
+++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -15,7 +15,7 @@
name: test
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32 }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' }
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' }
registers:
diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
index 1771d6f..d3c4223 100644
--- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
@@ -19,7 +19,7 @@
frameInfo:
maxAlignment: 4
# CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
+# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' }
fixedStack:
- { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
stack:
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
index a893b08..445d1bd 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
@@ -51,8 +51,9 @@
maxAlignment: 16
# CHECK-LABEL: foo
# CHECK: stack:
-# CHECK: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
-# CHECK-NEXT: di-expression: '!10', di-location: '!11' }
+# CHECK: - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '!4', di-expression: '!10',
+# CHECK-NEXT: di-location: '!11' }
stack:
- { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
di-expression: '!7', di-location: '!8' }
diff --git a/llvm/test/CodeGen/MIR/X86/stack-objects.mir b/llvm/test/CodeGen/MIR/X86/stack-objects.mir
index 08b9ec0..608202e 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-objects.mir
@@ -21,9 +21,12 @@
frameInfo:
maxAlignment: 8
# CHECK: stack:
-# CHECK-NEXT: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
-# CHECK-NEXT: - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
-# CHECK-NEXT: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
+# CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
stack:
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
- { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
index 5e7d993..95efd97 100644
--- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
@@ -24,9 +24,11 @@
maxAlignment: 8
adjustsStack: true
# CHECK: stack:
-# CHECK-NEXT: - { id: 0, offset: -20, size: 4, alignment: 4 }
-# CHECK-NEXT: - { id: 1, offset: -32, size: 8, alignment: 8 }
-# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
+# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
+# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
stack:
- { id: 0, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -32, size: 8, alignment: 8 }
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
index e63bcf4..0d181f8 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -33,9 +33,9 @@
name: bar
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32 }
-# CHECK-NEXT: - { id: 1, class: gr32 }
-# CHECK-NEXT: - { id: 2, class: gr32 }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
@@ -67,9 +67,9 @@
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32 }
-# CHECK-NEXT: - { id: 1, class: gr32 }
-# CHECK-NEXT: - { id: 2, class: gr32 }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 2, class: gr32 }
- { id: 0, class: gr32 }