[PowerPC] Replace float load/store pair with integer load/store pair when it's only used in load/store
Replace float load/store pair with integer load/store pair when it's only used in load/store,
because float load/store instructions cost more cycles then integer load/store.
A typical scenario is when there is a call with more than 13 float arguments passing, we need pass them by stack.
So we need a load/store pair to do such memory operation if the variable is global variable.
Differential Revision: https://reviews.llvm.org/D64195
llvm-svn: 366775
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 97422c6..ff9423a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -834,6 +834,18 @@
return true;
}
+ bool isDesirableToTransformToIntegerOp(unsigned Opc,
+ EVT VT) const override {
+ // Only handle float load/store pair because float(fpr) load/store
+ // instruction has more cycles than integer(gpr) load/store in PPC.
+ if (Opc != ISD::LOAD && Opc != ISD::STORE)
+ return false;
+ if (VT != MVT::f32 && VT != MVT::f64)
+ return false;
+
+ return true;
+ }
+
// Returns true if the address of the global is stored in TOC entry.
bool isAccessedAsGotIndirect(SDValue N) const;
diff --git a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
index 6a8bd8e..17e71c5 100644
--- a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
+++ b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
@@ -54,27 +54,27 @@
; CHECK-NEXT: addis 3, 2, a10@toc@ha
; CHECK-NEXT: lfd 10, a10@toc@l(3)
; CHECK-NEXT: addis 3, 2, a11@toc@ha
+; CHECK-NEXT: addis 6, 2, a17@toc@ha
+; CHECK-NEXT: addis 5, 2, a16@toc@ha
+; CHECK-NEXT: addi 6, 6, a17@toc@l
+; CHECK-NEXT: addi 5, 5, a16@toc@l
+; CHECK-NEXT: lxvx 34, 0, 6
+; CHECK-NEXT: addis 4, 2, a15@toc@ha
+; CHECK-NEXT: lxvx 0, 0, 5
+; CHECK-NEXT: ld 4, a15@toc@l(4)
+; CHECK-NEXT: li 5, 168
; CHECK-NEXT: lfd 11, a11@toc@l(3)
; CHECK-NEXT: addis 3, 2, a12@toc@ha
; CHECK-NEXT: lfd 12, a12@toc@l(3)
; CHECK-NEXT: addis 3, 2, a13@toc@ha
; CHECK-NEXT: lfd 13, a13@toc@l(3)
; CHECK-NEXT: addis 3, 2, a14@toc@ha
-; CHECK-NEXT: lfd 0, a14@toc@l(3)
-; CHECK-NEXT: addis 3, 2, a15@toc@ha
-; CHECK-NEXT: addis 4, 2, a17@toc@ha
-; CHECK-NEXT: addi 4, 4, a17@toc@l
-; CHECK-NEXT: lxsd 2, a15@toc@l(3)
-; CHECK-NEXT: addis 3, 2, a16@toc@ha
-; CHECK-NEXT: addi 3, 3, a16@toc@l
-; CHECK-NEXT: lxvx 36, 0, 4
-; CHECK-NEXT: lxvx 35, 0, 3
-; CHECK-NEXT: li 3, 168
-; CHECK-NEXT: stxvx 36, 1, 3
-; CHECK-NEXT: li 3, 152
-; CHECK-NEXT: stxvx 35, 1, 3
-; CHECK-NEXT: stxsd 2, 144(1)
-; CHECK-NEXT: stfd 0, 136(1)
+; CHECK-NEXT: ld 3, a14@toc@l(3)
+; CHECK-NEXT: stxvx 34, 1, 5
+; CHECK-NEXT: li 5, 152
+; CHECK-NEXT: stxvx 0, 1, 5
+; CHECK-NEXT: std 4, 144(1)
+; CHECK-NEXT: std 3, 136(1)
; CHECK-NEXT: bl _Z3fooddddddddddddddd
; CHECK-NEXT: nop
; CHECK-NEXT: li 3, 0
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll b/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll
index 710077d..a71ea80 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll
@@ -52,7 +52,7 @@
ret void
}
; CHECK: @caller2
-; CHECK: stfs {{[0-9]+}}, 156(1)
+; CHECK: std {{[0-9]+}}, 16(1)
; CHECK: bl test2
declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll
index 8e853cd..9eac7d0 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll
@@ -52,7 +52,7 @@
ret void
}
; CHECK: @caller2
-; CHECK: stfs {{[0-9]+}}, 136({{[0-9]+}})
+; CHECK: std {{[0-9]+}}, 16({{[0-9]+}})
; CHECK: bl test2
declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
diff --git a/llvm/test/CodeGen/PowerPC/pwr7-gt-nop.ll b/llvm/test/CodeGen/PowerPC/pwr7-gt-nop.ll
index be8578c..b7c899c 100644
--- a/llvm/test/CodeGen/PowerPC/pwr7-gt-nop.ll
+++ b/llvm/test/CodeGen/PowerPC/pwr7-gt-nop.ll
@@ -16,12 +16,12 @@
store float %2, float* %d, align 4
ret void
-; CHECK: lfs [[REG1:[0-9]+]], 0(4)
-; CHECK: stfs [[REG1]], 0(3)
-; CHECK: lfs [[REG2:[0-9]+]], 0(5)
-; CHECK: stfs [[REG2]], 0(4)
-; CHECK: lfs [[REG3:[0-9]+]], 0(3)
-; CHECK: stfs [[REG3]], 0(6)
+; CHECK: lwz [[REG1:[0-9]+]], 0(4)
+; CHECK: stw [[REG1]], 0(3)
+; CHECK: lwz [[REG2:[0-9]+]], 0(5)
+; CHECK: stw [[REG2]], 0(4)
+; CHECK: lwz [[REG3:[0-9]+]], 0(3)
+; CHECK: stw [[REG3]], 0(6)
; CHECK: blr
}