Fix ARM encoding of non-return LDM instructions.
llvm-svn: 118732
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index ddf0c82..f03ef56 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -943,7 +943,7 @@
bits<16> dsts;
bits<4> Rn;
let Inst{27-25} = 0b100;
- let Inst{22} = 0; // S bit
+ let Inst{24-22} = 0b010;
let Inst{20} = 1; // L bit
let Inst{19-16} = Rn;
let Inst{15-0} = dsts;
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 9865ee5..f36a9fd 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1186,7 +1186,6 @@
"$Rn = $wb", []> {
bits<4> p;
let Inst{31-28} = p;
- let Inst{24-23} = 0b01;
let Inst{21} = 1;
}
@@ -1709,13 +1708,21 @@
def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoad_m,
- "ldm${amode}${p}\t$Rn, $dsts", "", []>;
+ "ldm${amode}${p}\t$Rn, $dsts", "", []> {
+ bits<4> p;
+ let Inst{31-28} = p;
+ let Inst{21} = 0;
+}
def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
"ldm${amode}${p}\t$Rn!, $dsts",
- "$Rn = $wb", []>;
+ "$Rn = $wb", []> {
+ bits<4> p;
+ let Inst{31-28} = p;
+ let Inst{21} = 1;
+}
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,