For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero.
llvm-svn: 118587
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 7b0bf12..bd799f2 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -277,6 +277,9 @@
// ROR - 11
switch (ShOp) {
default: llvm_unreachable("Unknown shift opc!");
+ case ARM_AM::no_shift:
+ assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
+ // fall through
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x1; break;
case ARM_AM::asr: SBits = 0x2; break;