[RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.
Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)
Differential Revision: https://reviews.llvm.org/D41225
Patch by Mario Werner.
llvm-svn: 320797
diff --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index c289dc3..5c89cbe 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -11,55 +11,55 @@
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beq a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_1
+; RV32I-NEXT: j .LBB0_1
; RV32I-NEXT: .LBB0_1: # %test2
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bne a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_2
+; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_2: # %test3
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: blt a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_3
+; RV32I-NEXT: j .LBB0_3
; RV32I-NEXT: .LBB0_3: # %test4
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bge a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_4
+; RV32I-NEXT: j .LBB0_4
; RV32I-NEXT: .LBB0_4: # %test5
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bltu a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_5
+; RV32I-NEXT: j .LBB0_5
; RV32I-NEXT: .LBB0_5: # %test6
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bgeu a3, a0, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_6
+; RV32I-NEXT: j .LBB0_6
; RV32I-NEXT: .LBB0_6: # %test7
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: blt a0, a3, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_7
+; RV32I-NEXT: j .LBB0_7
; RV32I-NEXT: .LBB0_7: # %test8
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bge a0, a3, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_8
+; RV32I-NEXT: j .LBB0_8
; RV32I-NEXT: .LBB0_8: # %test9
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bltu a0, a3, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_9
+; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_9: # %test10
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bgeu a0, a3, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_10
+; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_10: # %test11
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: andi a0, a2, 1
-; RV32I-NEXT: bne a0, zero, .LBB0_12
-; RV32I-NEXT: jal zero, .LBB0_11
+; RV32I-NEXT: bnez a0, .LBB0_12
+; RV32I-NEXT: j .LBB0_11
; RV32I-NEXT: .LBB0_11: # %test12
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: .LBB0_12: # %end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %val1, %a