[PowerPC] add ftrunc vector tests; NFC
Baseline tests for vectors as suggested in D44909.
llvm-svn: 328682
diff --git a/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
new file mode 100644
index 0000000..99f21a1
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
+
+define <4 x float> @truncf32(<4 x float> %a) {
+; CHECK-LABEL: truncf32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvcvspsxws 0, 34
+; CHECK-NEXT: xvcvsxwsp 34, 0
+; CHECK-NEXT: blr
+ %t0 = fptosi <4 x float> %a to <4 x i32>
+ %t1 = sitofp <4 x i32> %t0 to <4 x float>
+ ret <4 x float> %t1
+}
+
+define <2 x double> @truncf64(<2 x double> %a) {
+; CHECK-LABEL: truncf64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvcvdpsxds 34, 34
+; CHECK-NEXT: xvcvsxddp 34, 34
+; CHECK-NEXT: blr
+ %t0 = fptosi <2 x double> %a to <2 x i64>
+ %t1 = sitofp <2 x i64> %t0 to <2 x double>
+ ret <2 x double> %t1
+}
+
+define <4 x float> @truncf32u(<4 x float> %a) {
+; CHECK-LABEL: truncf32u:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvcvspuxws 0, 34
+; CHECK-NEXT: xvcvuxwsp 34, 0
+; CHECK-NEXT: blr
+ %t0 = fptoui <4 x float> %a to <4 x i32>
+ %t1 = uitofp <4 x i32> %t0 to <4 x float>
+ ret <4 x float> %t1
+}
+
+define <2 x double> @truncf64u(<2 x double> %a) {
+; CHECK-LABEL: truncf64u:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvcvdpuxds 34, 34
+; CHECK-NEXT: xvcvuxddp 34, 34
+; CHECK-NEXT: blr
+ %t0 = fptoui <2 x double> %a to <2 x i64>
+ %t1 = uitofp <2 x i64> %t0 to <2 x double>
+ ret <2 x double> %t1
+}
+