commit 595683da00a7d4725de12e11e70abea7e73127b9
author Robert Khasanov <rob.khasanov@gmail.com> Mon Jul 28 13:46:45 2014 +0000
committer Robert Khasanov <rob.khasanov@gmail.com> Mon Jul 28 13:46:45 2014 +0000
tree f83389dc20b888023bfda579e9c7a4acb9c425ee
parent 544f45b39f75e06df35f5c3144ba746e49c386c3

[SKX] Enabling mask logic instructions: encoding, lowering
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 214081

llvm/utils/TableGen/X86RecognizableInstr.cpp

diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 2261dc8..4068b8d 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -1117,6 +1117,8 @@
   ENCODING("VK4",             ENCODING_VVVV)
   ENCODING("VK8",             ENCODING_VVVV)
   ENCODING("VK16",            ENCODING_VVVV)
+  ENCODING("VK32",            ENCODING_VVVV)
+  ENCODING("VK64",            ENCODING_VVVV)
   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
   llvm_unreachable("Unhandled VEX.vvvv register encoding");
 }