commit 5965bd19f85f1fa1d80e3bba42dc7954d0ff5f73
author Nate Begeman <natebegeman@mac.com> Fri Feb 17 05:43:56 2006 +0000
committer Nate Begeman <natebegeman@mac.com> Fri Feb 17 05:43:56 2006 +0000
tree ec5b69adc0a9b29157bfccc8676805738ff6f1c0
parent 9ec392b2aa6ad02cfba5068ec163af7a2adc0476

kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm/lib/Target/Sparc/SparcInstrInfo.td

diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 6a1b012..3d61063 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -453,16 +453,20 @@
                    
 def ADDCCrr : F3_1<2, 0b010000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "addcc $b, $c, $dst", []>;
+                   "addcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
 def ADDCCri : F3_2<2, 0b010000,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "addcc $b, $c, $dst", []>;
+                   "addcc $b, $c, $dst", 
+                   [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
 def ADDXrr  : F3_1<2, 0b001000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "addx $b, $c, $dst", []>;
+                   "addx $b, $c, $dst",
+                   [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
 def ADDXri  : F3_2<2, 0b001000,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "addx $b, $c, $dst", []>;
+                   "addx $b, $c, $dst",
+                   [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, 
@@ -475,10 +479,12 @@
                    [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
 def SUBXrr  : F3_1<2, 0b001100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "subx $b, $c, $dst", []>;
+                   "subx $b, $c, $dst",
+                   [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
 def SUBXri  : F3_2<2, 0b001100,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "subx $b, $c, $dst", []>;
+                   "subx $b, $c, $dst",
+                   [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
 def SUBCCrr : F3_1<2, 0b010100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "subcc $b, $c, $dst",
@@ -866,6 +872,12 @@
 def : Pat<(i32 imm:$val),
           (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 
+// subc
+def : Pat<(subc IntRegs:$b, IntRegs:$c),
+          (SUBCCrr IntRegs:$b, IntRegs:$c)>;
+def : Pat<(subc IntRegs:$b, simm13:$val),
+          (SUBCCri IntRegs:$b, imm:$val)>;
+
 // Global addresses, constant pool entries
 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;