[TargetLowering] Simplify expansion of S{ADD,SUB}O
ISD::SADDO uses the suggested sequence described in the section ยง2.4 of
the RISCV Spec v2.2. ISD::SSUBO uses the dual approach but checking for
(non-zero) positive.
Differential Revision: https://reviews.llvm.org/D47927
llvm-svn: 373187
diff --git a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll
index 8d72082..4358fb5 100644
--- a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll
+++ b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll
@@ -10,17 +10,11 @@
define i1 @sadd(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: sadd:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi a3, zero, -1
-; RV32I-NEXT: slt a4, a3, a1
-; RV32I-NEXT: slt a5, a3, a0
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: seqz a4, a4
-; RV32I-NEXT: add a1, a0, a1
-; RV32I-NEXT: slt a0, a3, a1
-; RV32I-NEXT: xor a0, a5, a0
-; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: and a0, a4, a0
-; RV32I-NEXT: sw a1, 0(a2)
+; RV32I-NEXT: add a3, a0, a1
+; RV32I-NEXT: slt a0, a3, a0
+; RV32I-NEXT: slti a1, a1, 0
+; RV32I-NEXT: xor a0, a1, a0
+; RV32I-NEXT: sw a3, 0(a2)
; RV32I-NEXT: ret
entry:
%x = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
@@ -33,16 +27,10 @@
define i1 @ssub(i32 %a, i32 %b, i32* %c) nounwind {
; RV32I-LABEL: ssub:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: addi a3, zero, -1
-; RV32I-NEXT: slt a4, a3, a1
-; RV32I-NEXT: slt a5, a3, a0
-; RV32I-NEXT: xor a4, a5, a4
-; RV32I-NEXT: snez a4, a4
+; RV32I-NEXT: sgtz a3, a1
; RV32I-NEXT: sub a1, a0, a1
-; RV32I-NEXT: slt a0, a3, a1
-; RV32I-NEXT: xor a0, a5, a0
-; RV32I-NEXT: snez a0, a0
-; RV32I-NEXT: and a0, a4, a0
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: xor a0, a3, a0
; RV32I-NEXT: sw a1, 0(a2)
; RV32I-NEXT: ret
entry: