[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine
r343712 performed this optimisation during instruction selection. As Eli
Friedman pointed out in post-commit review, implementing this as a DAGCombine
might allow opportunities for further optimisations.
llvm-svn: 343741
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e61086b..e355b20 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -96,18 +96,6 @@
ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
return;
}
- case RISCVISD::SplitF64: {
- // If the input to SplitF64 is just BuildPairF64 then the operation is
- // redundant. Instead, use BuildPairF64's operands directly. This pattern
- // can't be written in tablegen due to the multiple outputs.
- SDValue Op0 = Node->getOperand(0);
- if (Op0->getOpcode() != RISCVISD::BuildPairF64)
- break;
- ReplaceUses(SDValue(Node, 0), Op0.getOperand(0));
- ReplaceUses(SDValue(Node, 1), Op0.getOperand(1));
- CurDAG->RemoveDeadNode(Node);
- return;
- }
}
// Select the default instruction.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6956975..550c906 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -494,6 +494,24 @@
return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
}
+SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ switch (N->getOpcode()) {
+ default:
+ break;
+ case RISCVISD::SplitF64: {
+ // If the input to SplitF64 is just BuildPairF64 then the operation is
+ // redundant. Instead, use BuildPairF64's operands directly.
+ SDValue Op0 = N->getOperand(0);
+ if (Op0->getOpcode() != RISCVISD::BuildPairF64)
+ break;
+ return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
+ }
+ }
+
+ return SDValue();
+}
+
static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
MachineBasicBlock *BB) {
assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index e219511..47dbc1a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -58,6 +58,8 @@
// Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+ SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+
// This method returns the name of a target specific DAG node.
const char *getTargetNodeName(unsigned Opcode) const override;