commit 5ae5f817207206f7d8401e40840283bf0625844c
author Andrew Lenharth <andrewl@lenharth.org> Wed Jan 26 21:54:09 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Wed Jan 26 21:54:09 2005 +0000
tree 0a2cc474190e5e10ed92d1402dffcf955c35c356
parent 651ffb1df84c54e291bcedac6a9e6a21d883d12d

 initial fp support

llvm-svn: 19847

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 9bb9acc..1a730b3 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,7 @@
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == Alpha::BIS) {  // or r1, r2, r2
+  if (oc == Alpha::BIS || oc == Alpha::CPYS) {  // or r1, r2, r2 // cpys r1 r2 r2
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&