GlobalISel: Change representation of shuffle masks
Currently shufflemasks get emitted as any other constant, and you end
up with a bunch of virtual registers of G_CONSTANT with a
G_BUILD_VECTOR. The AArch64 selector then asserts on anything that
doesn't fit this pattern. This isn't an ideal representation, and
should avoid legalization and have fewer opportunities for a
representational error.
Rather than invent a new shuffle mask operand type, similar to what
ShuffleVectorSDNode does, just track the original IR Constant mask
operand. I don't completely like the idea of adding another link to
the IR, but MIR is already quite dependent on IR constants already,
and this will allow sharing the shuffle mask utility functions with
the IR.
llvm-svn: 368704
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 4899bd3..ad5c617 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -249,6 +249,7 @@
.Case("successors", MIToken::kw_successors)
.Case("floatpred", MIToken::kw_floatpred)
.Case("intpred", MIToken::kw_intpred)
+ .Case("shufflemask", MIToken::kw_shufflemask)
.Case("pre-instr-symbol", MIToken::kw_pre_instr_symbol)
.Case("post-instr-symbol", MIToken::kw_post_instr_symbol)
.Case("unknown-size", MIToken::kw_unknown_size)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 0fe3f9f..200f9d0 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -117,6 +117,7 @@
kw_successors,
kw_floatpred,
kw_intpred,
+ kw_shufflemask,
kw_pre_instr_symbol,
kw_post_instr_symbol,
kw_unknown_size,
@@ -146,6 +147,7 @@
IntegerLiteral,
FloatingPointLiteral,
HexLiteral,
+ VectorLiteral,
VirtualRegister,
ConstantPoolItem,
JumpTableIndex,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 89eaaf6..a8fa2f1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -451,6 +451,7 @@
bool parseBlockAddressOperand(MachineOperand &Dest);
bool parseIntrinsicOperand(MachineOperand &Dest);
bool parsePredicateOperand(MachineOperand &Dest);
+ bool parseShuffleMaskOperand(MachineOperand &Dest);
bool parseTargetIndexOperand(MachineOperand &Dest);
bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
@@ -2285,6 +2286,49 @@
return false;
}
+bool MIParser::parseShuffleMaskOperand(MachineOperand &Dest) {
+ assert(Token.is(MIToken::kw_shufflemask));
+
+ lex();
+ if (expectAndConsume(MIToken::lparen))
+ return error("expected syntax shufflemask(<integer or undef>, ...)");
+
+ SmallVector<Constant *, 32> ShufMask;
+ LLVMContext &Ctx = MF.getFunction().getContext();
+ Type *I32Ty = Type::getInt32Ty(Ctx);
+
+ bool AllZero = true;
+ bool AllUndef = true;
+
+ do {
+ if (Token.is(MIToken::kw_undef)) {
+ ShufMask.push_back(UndefValue::get(I32Ty));
+ AllZero = false;
+ } else if (Token.is(MIToken::IntegerLiteral)) {
+ AllUndef = false;
+ const APSInt &Int = Token.integerValue();
+ if (!Int.isNullValue())
+ AllZero = false;
+ ShufMask.push_back(ConstantInt::get(I32Ty, Int.getExtValue()));
+ } else
+ return error("expected integer constant");
+
+ lex();
+ } while (consumeIfPresent(MIToken::comma));
+
+ if (expectAndConsume(MIToken::rparen))
+ return error("shufflemask should be terminated by ')'.");
+
+ if (AllZero || AllUndef) {
+ VectorType *VT = VectorType::get(I32Ty, ShufMask.size());
+ Constant *C = AllZero ? Constant::getNullValue(VT) : UndefValue::get(VT);
+ Dest = MachineOperand::CreateShuffleMask(C);
+ } else
+ Dest = MachineOperand::CreateShuffleMask(ConstantVector::get(ShufMask));
+
+ return false;
+}
+
bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) {
assert(Token.is(MIToken::kw_target_index));
lex();
@@ -2432,6 +2476,8 @@
case MIToken::kw_floatpred:
case MIToken::kw_intpred:
return parsePredicateOperand(Dest);
+ case MIToken::kw_shufflemask:
+ return parseShuffleMaskOperand(Dest);
case MIToken::Error:
return true;
case MIToken::Identifier: