commit 5b3b9d7052ca360165ed92c4382fe30ed18ed4bb
author Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 19:52:25 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 19:52:25 2005 +0000
tree 9d9e919fd3cb83d92645b65d661eabf924b5260a
parent 5278ca3fa2a4d2f12fdab2b9559f2e1a73010829

Fix a bunch more alpha regressions

llvm-svn: 24304

llvm/lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 791fced..3218f03 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1533,7 +1533,7 @@
             N.getOperand(0).getValueType() == MVT::f32 &&
             "only f32 to f64 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
+    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::ConstantFP: