commit 5bf3b20e9958bb03c68e2a0a739f335ea0086c47
author Alex Bradbury <asb@lowrisc.org> Thu Oct 04 14:30:03 2018 +0000
committer Alex Bradbury <asb@lowrisc.org> Thu Oct 04 14:30:03 2018 +0000
tree 02ea754250f0edc2c3d24a37b101edb9752aa2cd
parent 422f7246183b41b9dbe04e93e28edcdaf39e0c22

[RISCV] Remove overzealous is64Bit checks

lowerGlobalAddress, lowerBlockAddress, and insertIndirectBranch contain 
overzealous checks for is64Bit. These functions are all safe as-implemented 
for RV64.

llvm-svn: 343781

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 327e4a7..76c7436 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -362,9 +362,8 @@
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
-  const auto &STI = MF->getSubtarget<RISCVSubtarget>();
 
-  if (TM.isPositionIndependent() || STI.is64Bit())
+  if (TM.isPositionIndependent())
     report_fatal_error("Unable to insert indirect branch");
 
   if (!isInt<32>(BrOffset))