commit 5c73e1f85c5d37a5b037c70f3c112eec5646acb3
author Andrew Kaylor <andrew.kaylor@intel.com> Tue Mar 24 23:37:10 2015 +0000
committer Andrew Kaylor <andrew.kaylor@intel.com> Tue Mar 24 23:37:10 2015 +0000
tree cf1eb4ad55c4752463a5e1408ba228555d16d03c
parent 5a07bb8b5f64368fe35d32d9653b5157a0d4b18b

Disabling warnings for MSVC build to enable /W4 use.

Differential Revision: http://reviews.llvm.org/D8572

llvm-svn: 233133

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 0a6be1a..5d461d5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -113,9 +113,8 @@
   const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
   unsigned Reg = DefMO.getReg();
 
-  const TargetRegisterInfo *TRI = &getRegisterInfo();
   bool IsRegCR;
-  if (TRI->isVirtualRegister(Reg)) {
+  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
     const MachineRegisterInfo *MRI =
       &DefMI->getParent()->getParent()->getRegInfo();
     IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||