[AArch64] Fix handling of zero immediate in fmov instructions
Currently fmov #0 with a vector destination is handle incorrectly and results in
fmov #-1.9375 being emitted but should instead give an error. This is due to the
way we cope with fmov #0 with a scalar destination being an alias of fmov zr, so
fix this by actually doing it through an alias.
Differential Revision: https://reviews.llvm.org/D31949
llvm-svn: 300830
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 347cffe..d7bbc2b 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2116,10 +2116,15 @@
uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
Val = AArch64_AM::getFP64Imm(APInt(64, IntVal));
- // Check for out of range values. As an exception, we let Zero through,
- // as we handle that special case in post-processing before matching in
- // order to use the zero register for it.
- if (Val == -1 && !RealVal.isPosZero()) {
+ // Check for out of range values. As an exception we let Zero through,
+ // but as tokens instead of an FPImm so that it can be matched by the
+ // appropriate alias if one exists.
+ if (RealVal.isPosZero()) {
+ Parser.Lex(); // Eat the token.
+ Operands.push_back(AArch64Operand::CreateToken("#0", false, S, getContext()));
+ Operands.push_back(AArch64Operand::CreateToken(".0", false, S, getContext()));
+ return MatchOperand_Success;
+ } else if (Val == -1) {
TokError("expected compatible register or floating-point constant");
return MatchOperand_ParseFail;
}
@@ -3646,21 +3651,6 @@
}
}
- // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
- if (NumOperands == 3 && Tok == "fmov") {
- AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]);
- AArch64Operand &ImmOp = static_cast<AArch64Operand &>(*Operands[2]);
- if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) {
- unsigned zreg =
- !AArch64MCRegisterClasses[AArch64::FPR64RegClassID].contains(
- RegOp.getReg())
- ? AArch64::WZR
- : AArch64::XZR;
- Operands[2] = AArch64Operand::CreateReg(zreg, false, Op.getStartLoc(),
- Op.getEndLoc(), getContext());
- }
- }
-
MCInst Inst;
// First try to match against the secondary set of tables containing the
// short-form NEON instructions (e.g. "fadd.2s v0, v1, v2").