commit 5cdacea29719082c4c9ec7c543486c4f81c25bd4
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Wed Jul 24 16:21:18 2019 +0000
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Wed Jul 24 16:21:18 2019 +0000
tree 0b155493c292dd6b2579bca9c63d2c91880c3b07
parent 0b7f2263118cb108467e3afdb8fda332735c1e12

[AMDGPU] Add all vgpr classes to asm parser

Differential Revision: https://reviews.llvm.org/D65158

llvm-svn: 366917

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index cb2d37a..b51858e 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -275,8 +275,10 @@
            isRegClass(AMDGPU::VReg_64RegClassID) ||
            isRegClass(AMDGPU::VReg_96RegClassID) ||
            isRegClass(AMDGPU::VReg_128RegClassID) ||
+           isRegClass(AMDGPU::VReg_160RegClassID) ||
            isRegClass(AMDGPU::VReg_256RegClassID) ||
-           isRegClass(AMDGPU::VReg_512RegClassID);
+           isRegClass(AMDGPU::VReg_512RegClassID) ||
+           isRegClass(AMDGPU::VReg_1024RegClassID);
   }
 
   bool isVReg32() const {
@@ -1872,8 +1874,10 @@
       case 2: return AMDGPU::VReg_64RegClassID;
       case 3: return AMDGPU::VReg_96RegClassID;
       case 4: return AMDGPU::VReg_128RegClassID;
+      case 5: return AMDGPU::VReg_160RegClassID;
       case 8: return AMDGPU::VReg_256RegClassID;
       case 16: return AMDGPU::VReg_512RegClassID;
+      case 32: return AMDGPU::VReg_1024RegClassID;
     }
   } else if (Is == IS_TTMP) {
     switch (RegWidth) {