[CodeGen] Print global addresses as @foo in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.
Also print target flags in the MIR format since most of them are used on
global address operands.
Only debug syntax is affected.
llvm-svn: 320682
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 053ab60..f625be3 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -161,7 +161,6 @@
void printIRValueReference(const Value &V);
void printStackObjectReference(int FrameIndex);
void printOffset(int64_t Offset);
- void printTargetFlags(const MachineOperand &Op);
void print(const MachineInstr &MI, unsigned OpIdx,
const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
LLT TypeToPrint, bool PrintDef = true);
@@ -778,72 +777,15 @@
OS << " + " << Offset;
}
-static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
- auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
- for (const auto &I : Flags) {
- if (I.first == TF) {
- return I.second;
- }
- }
- return nullptr;
-}
-
-void MIPrinter::printTargetFlags(const MachineOperand &Op) {
- if (!Op.getTargetFlags())
- return;
- const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
- assert(TII && "expected instruction info");
- auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
- OS << "target-flags(";
- const bool HasDirectFlags = Flags.first;
- const bool HasBitmaskFlags = Flags.second;
- if (!HasDirectFlags && !HasBitmaskFlags) {
- OS << "<unknown>) ";
- return;
- }
- if (HasDirectFlags) {
- if (const auto *Name = getTargetFlagName(TII, Flags.first))
- OS << Name;
- else
- OS << "<unknown target flag>";
- }
- if (!HasBitmaskFlags) {
- OS << ") ";
- return;
- }
- bool IsCommaNeeded = HasDirectFlags;
- unsigned BitMask = Flags.second;
- auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
- for (const auto &Mask : BitMasks) {
- // Check if the flag's bitmask has the bits of the current mask set.
- if ((BitMask & Mask.first) == Mask.first) {
- if (IsCommaNeeded)
- OS << ", ";
- IsCommaNeeded = true;
- OS << Mask.second;
- // Clear the bits which were serialized from the flag's bitmask.
- BitMask &= ~(Mask.first);
- }
- }
- if (BitMask) {
- // When the resulting flag's bitmask isn't zero, we know that we didn't
- // serialize all of the bit flags.
- if (IsCommaNeeded)
- OS << ", ";
- OS << "<unknown bitmask target flag>";
- }
- OS << ") ";
-}
-
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
const TargetRegisterInfo *TRI,
bool ShouldPrintRegisterTies, LLT TypeToPrint,
bool PrintDef) {
const MachineOperand &Op = MI.getOperand(OpIdx);
- printTargetFlags(Op);
switch (Op.getType()) {
case MachineOperand::MO_Immediate:
if (MI.isOperandSubregIdx(OpIdx)) {
+ MachineOperand::printTargetFlags(OS, Op);
MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
break;
}
@@ -854,7 +796,8 @@
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_TargetIndex:
case MachineOperand::MO_JumpTableIndex:
- case MachineOperand::MO_ExternalSymbol: {
+ case MachineOperand::MO_ExternalSymbol:
+ case MachineOperand::MO_GlobalAddress: {
unsigned TiedOperandIdx = 0;
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -869,10 +812,6 @@
case MachineOperand::MO_FrameIndex:
printStackObjectReference(Op.getIndex());
break;
- case MachineOperand::MO_GlobalAddress:
- Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
- printOffset(Op.getOffset());
- break;
case MachineOperand::MO_BlockAddress:
OS << "blockaddress(";
Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 6882e9f..7ffdbea 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -401,6 +401,16 @@
return nullptr;
}
+static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
+ auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
+ for (const auto &I : Flags) {
+ if (I.first == TF) {
+ return I.second;
+ }
+ }
+ return nullptr;
+}
+
void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
const TargetRegisterInfo *TRI) {
OS << "%subreg.";
@@ -410,6 +420,58 @@
OS << Index;
}
+void MachineOperand::printTargetFlags(raw_ostream &OS,
+ const MachineOperand &Op) {
+ if (!Op.getTargetFlags())
+ return;
+ const MachineFunction *MF = getMFIfAvailable(Op);
+ if (!MF)
+ return;
+
+ const auto *TII = MF->getSubtarget().getInstrInfo();
+ assert(TII && "expected instruction info");
+ auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
+ OS << "target-flags(";
+ const bool HasDirectFlags = Flags.first;
+ const bool HasBitmaskFlags = Flags.second;
+ if (!HasDirectFlags && !HasBitmaskFlags) {
+ OS << "<unknown>) ";
+ return;
+ }
+ if (HasDirectFlags) {
+ if (const auto *Name = getTargetFlagName(TII, Flags.first))
+ OS << Name;
+ else
+ OS << "<unknown target flag>";
+ }
+ if (!HasBitmaskFlags) {
+ OS << ") ";
+ return;
+ }
+ bool IsCommaNeeded = HasDirectFlags;
+ unsigned BitMask = Flags.second;
+ auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
+ for (const auto &Mask : BitMasks) {
+ // Check if the flag's bitmask has the bits of the current mask set.
+ if ((BitMask & Mask.first) == Mask.first) {
+ if (IsCommaNeeded)
+ OS << ", ";
+ IsCommaNeeded = true;
+ OS << Mask.second;
+ // Clear the bits which were serialized from the flag's bitmask.
+ BitMask &= ~(Mask.first);
+ }
+ }
+ if (BitMask) {
+ // When the resulting flag's bitmask isn't zero, we know that we didn't
+ // serialize all of the bit flags.
+ if (IsCommaNeeded)
+ OS << ", ";
+ OS << "<unknown bitmask target flag>";
+ }
+ OS << ") ";
+}
+
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
@@ -425,6 +487,7 @@
unsigned TiedOperandIdx,
const TargetRegisterInfo *TRI,
const TargetIntrinsicInfo *IntrinsicInfo) const {
+ printTargetFlags(OS, *this);
switch (getType()) {
case MachineOperand::MO_Register: {
unsigned Reg = getReg();
@@ -528,11 +591,8 @@
OS << printJumpTableEntryReference(getIndex());
break;
case MachineOperand::MO_GlobalAddress:
- OS << "<ga:";
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
- if (getOffset())
- OS << "+" << getOffset();
- OS << '>';
+ printOffset(OS, getOffset());
break;
case MachineOperand::MO_ExternalSymbol: {
StringRef Name = getSymbolName();
@@ -608,8 +668,6 @@
break;
}
}
- if (unsigned TF = getTargetFlags())
- OS << "[TF=" << TF << ']';
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)