Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183494
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
index 55b45d0..84b8e6d 100644
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h
@@ -43,7 +43,7 @@
/// setting the CTR register then branching through it within a dispatch group),
/// or storing then loading from the same address within a dispatch group.
class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
- const TargetInstrInfo &TII;
+ const TargetMachine &TM;
unsigned NumIssued; // Number of insts issued, including advanced cycles.
@@ -64,7 +64,7 @@
unsigned NumStores;
public:
- PPCHazardRecognizer970(const TargetInstrInfo &TII);
+ PPCHazardRecognizer970(const TargetMachine &TM);
virtual HazardType getHazardType(SUnit *SU, int Stalls);
virtual void EmitInstruction(SUnit *SU);
virtual void AdvanceCycle();