When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.
llvm-svn: 172322
diff --git a/llvm/test/CodeGen/PowerPC/vec_extload.ll b/llvm/test/CodeGen/PowerPC/vec_extload.ll
index 42334d7..998645d 100644
--- a/llvm/test/CodeGen/PowerPC/vec_extload.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extload.ll
@@ -15,7 +15,7 @@
ret <16 x i8> %c
}
; CHECK: v16si8_sext_in_reg:
-; CHECK: vsrb
+; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
@@ -37,7 +37,7 @@
ret <8 x i16> %c
}
; CHECK: v8si16_sext_in_reg:
-; CHECK: vsrh
+; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
@@ -61,7 +61,7 @@
ret <4 x i32> %c
}
; CHECK: v4si32_sext_in_reg:
-; CHECK: vsrw
+; CHECK: vslw
; CHECK: vsraw
; CHECK: blr