[WebAssembly] Implement vector sext_inreg and tests with comparisons
Summary: Depends on D53251.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53252
llvm-svn: 344826
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 0b09da7..711d42a 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -613,7 +613,8 @@
defm _#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
[(set (out_t V128:$dst),
- (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond))],
+ (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
+ )],
vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
}
@@ -621,15 +622,15 @@
int step = 1> {
defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
- !add(baseInst, step)>;
+ !add(baseInst, step)>;
defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
- !add(!add(baseInst, step), step)>;
+ !add(!add(baseInst, step), step)>;
}
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
- !add(baseInst, 1)>;
+ !add(baseInst, 1)>;
}
// Equality: eq