Improve lowering of sext to i128 on SPU.
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
llvm-svn: 116701
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 38b9f4e..2a82988 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2642,11 +2642,16 @@
DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
DAG.getConstant(31, MVT::i32));
+ // reinterpret as a i128 (SHUFB requires it). This gets lowered away.
+ SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+ dl, Op0VT, Op0,
+ DAG.getTargetConstant(
+ SPU::GPRCRegClass.getID(),
+ MVT::i32)), 0);
// Shuffle bytes - Copy the sign bits into the upper 64 bits
// and the input value into the lower 64 bits.
SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
- DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
-
+ extended, sraVal, shufMask);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
}
diff --git a/llvm/test/CodeGen/CellSPU/sext128.ll b/llvm/test/CodeGen/CellSPU/sext128.ll
index 0c0b359..8a5b609 100644
--- a/llvm/test/CodeGen/CellSPU/sext128.ll
+++ b/llvm/test/CodeGen/CellSPU/sext128.ll
@@ -12,6 +12,7 @@
; CHECK: long 269488144
; CHECK: long 66051
; CHECK: long 67438087
+; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb
@@ -25,6 +26,7 @@
; CHECK: long 269488144
; CHECK: long 269488144
; CHECK: long 66051
+; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb
@@ -39,6 +41,7 @@
; CHECK: long 269488144
; CHECK: long 269488144
; CHECK: long 66051
+; CHECK-NOT: rotqmbyi
; CHECK: rotmai
; CHECK: lqa
; CHECK: shufb