commit 5f35afb0f18a8ee6171ae012fe52219460d03322
author Andrew Trick <atrick@apple.com> Thu Oct 11 05:37:06 2012 +0000
committer Andrew Trick <atrick@apple.com> Thu Oct 11 05:37:06 2012 +0000
tree de3a5f2a84d4a8c0d7ea0c7984e8165999bbcb7f
parent 49ac81ac68228e51cd1e8ce5c0b7bcaaed2e9bda

misched: Handle "transient" non-instructions.

llvm-svn: 165701

llvm/lib/CodeGen/TargetInstrInfoImpl.cpp

diff --git a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
index 8ed66f7..4439192 100644
--- a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -563,6 +563,8 @@
 /// Return the default expected latency for a def based on it's opcode.
 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
                                             const MachineInstr *DefMI) const {
+  if (DefMI->isTransient())
+    return 0;
   if (DefMI->mayLoad())
     return SchedModel->LoadLatency;
   if (isHighLatencyDef(DefMI->getOpcode()))