commit 5f629318fa7da04a2594658e9ba3c01b62463e2b
author Ruchira Sasanka <sasanka@students.uiuc.edu> Thu Oct 18 22:38:52 2001 +0000
committer Ruchira Sasanka <sasanka@students.uiuc.edu> Thu Oct 18 22:38:52 2001 +0000
tree e0ae5f2148e974e2beb580f6e6a118292c47ce4c
parent 0a2990a7c6282429af973e9c539b9991869dfbc9

Added support for condition code loading/stroing in methods cpReg2Reg etc.

llvm-svn: 911

llvm/lib/Target/Sparc/SparcRegClassInfo.cpp

diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
index ff01f35..3ff0779 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
@@ -42,7 +42,7 @@
       LR->setColor(  LR->getSuggestedColor() );
       return;
     }
-    else {                              // can't allocate the suggested col
+    else if ( DEBUG_RA ) {                // can't allocate the suggested col
       cerr << " Could NOT allocate the suggested color for LR ";
       LR->printSet(); cerr << endl;
     }
@@ -192,7 +192,7 @@
       LR->setColor(  LR->getSuggestedColor() );
       return;
     }
-    else {                              // can't allocate the suggested col
+    else if (DEBUG_RA)  {                 // can't allocate the suggested col
       cerr << " Could NOT allocate the suggested color for LR ";
       LR->printSet(); cerr << endl;
     }

llvm/lib/Target/Sparc/SparcRegInfo.cpp

diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 5756dc3..60f4203 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -621,6 +621,8 @@
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(ADD, 3);
     MI->SetMachineOperand(0, SrcReg, false);
     MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
@@ -664,6 +666,8 @@
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(STX, 3);
     MI->SetMachineOperand(0, DestPtrReg, false);
     MI->SetMachineOperand(1, SrcReg, false);
@@ -711,6 +715,8 @@
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(LDX, 3);
     MI->SetMachineOperand(0, SrcPtrReg, false);
     MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,