ARM stm/ldm instructions require more than one register in the register list.
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
llvm-svn: 121391
diff --git a/llvm/test/CodeGen/ARM/str_pre-2.ll b/llvm/test/CodeGen/ARM/str_pre-2.ll
index a79cf9b..4f9ba4d 100644
--- a/llvm/test/CodeGen/ARM/str_pre-2.ll
+++ b/llvm/test/CodeGen/ARM/str_pre-2.ll
@@ -4,8 +4,8 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
-; CHECK: push {lr}
-; CHECK: ldmia sp!, {pc}
+; CHECK: str lr, [sp, #-4]!
+; CHECK: ldr lr, [sp], #4
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a