[Hexagon] Improve scheduling heuristic for large basic blocks
This patch changes the isLatencyBound heuristic to look at the
path length based upon the number of packets needed to schedule
a basic block. For small basic blocks, the heuristic uses a small
threshold for isLatencyBound. For large basic blocks, the
heuristic uses a large threshold.
The goal is to increase the priority of an instruction in a small
basic block that has a large height or depth relative to the code
size. For large functions, the height and depth are ignored
because it increases the live range of a register and causes more
spills. That is, for large functions, it is more important to
schedule instructions when available, and attempt to keep the defs
and uses closer together.
Patch by Brendon Cahoon.
llvm-svn: 327987
diff --git a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
index 9d5c984..8ac333f4 100644
--- a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
@@ -32,6 +32,7 @@
UsesDotCur = nullptr;
DotCurPNum = -1;
UsesLoad = false;
+ PrefVectorStoreNew = nullptr;
RegDefs.clear();
}
@@ -80,6 +81,7 @@
DotCurPNum = -1;
}
UsesLoad = false;
+ PrefVectorStoreNew = nullptr;
PacketNum++;
RegDefs.clear();
}
@@ -89,8 +91,14 @@
/// bank conflict. Case 2 - if a packet contains a dot cur instruction, then we
/// prefer the instruction that can use the dot cur result. However, if the use
/// is not scheduled in the same packet, then prefer other instructions in the
-/// subsequent packet.
+/// subsequent packet. Case 3 - we prefer a vector store that can be converted
+/// to a .new store. The packetizer will not generate the .new store if the
+/// store doesn't have resources to fit in the packet (but the .new store may
+/// have resources). We attempt to schedule the store as soon as possible to
+/// help packetize the two instructions together.
bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
+ if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)
+ return true;
if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
return true;
return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
@@ -144,4 +152,13 @@
}
UsesLoad = MI->mayLoad();
+
+ if (TII->isHVXVec(*MI) && !MI->mayLoad() && !MI->mayStore())
+ for (auto &S : SU->Succs)
+ if (S.isAssignedRegDep() && S.getLatency() == 0 &&
+ TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&
+ Resources->canReserveResources(*S.getSUnit()->getInstr())) {
+ PrefVectorStoreNew = S.getSUnit();
+ break;
+ }
}