commit 6023d5990d063ddf6df37bb54d9bd1d1752a3138
author Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Mon Mar 04 12:48:32 2019 +0000
committer Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> Mon Mar 04 12:48:32 2019 +0000
tree 547c106c168a930ec5a9aa2bda1c65af2b7e7eff
parent 9735d9011a70f3efe317ce20645f7e1cbe6c6888

[AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b32 and v_writelane_b32

See bug 40662: https://bugs.llvm.org/show_bug.cgi?id=40662

Reviewers: artem.tamazov, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D58713

llvm-svn: 355312

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index e172733..9612874 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -802,9 +802,11 @@
   switch (RCID) {
   case AMDGPU::SGPR_32RegClassID:
   case AMDGPU::VGPR_32RegClassID:
+  case AMDGPU::VRegOrLds_32RegClassID:
   case AMDGPU::VS_32RegClassID:
   case AMDGPU::SReg_32RegClassID:
   case AMDGPU::SReg_32_XM0RegClassID:
+  case AMDGPU::SRegOrLds_32RegClassID:
     return 32;
   case AMDGPU::SGPR_64RegClassID:
   case AMDGPU::VS_64RegClassID: