[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.
Patch by Sander De Smalen.
Reviewed by: rengolin
Differential Revision: https://reviews.llvm.org/D39087
llvm-svn: 317564
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index f6be8da..3b400c1 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -603,6 +603,11 @@
auto IsSubVec = [](MVT B, MVT P) -> bool {
if (!B.isVector() || !P.isVector())
return false;
+ // Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
+ // but until there are obvious use-cases for this, keep the
+ // types separate.
+ if (B.isScalableVector() != P.isScalableVector())
+ return false;
if (B.getVectorElementType() != P.getVectorElementType())
return false;
return B.getVectorNumElements() < P.getVectorNumElements();