[AMDGPU] Simplify negated condition
Optimize sequence:
%sel = V_CNDMASK_B32_e64 0, 1, %cc
%cmp = V_CMP_NE_U32 1, %1
$vcc = S_AND_B64 $exec, %cmp
S_CBRANCH_VCC[N]Z
=>
$vcc = S_ANDN2_B64 $exec, %cc
S_CBRANCH_VCC[N]Z
It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
rebuildSetCC().
Differential Revision: https://reviews.llvm.org/D55402
llvm-svn: 349003
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index e53d876..a61e6d7 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -103,6 +103,122 @@
return SaveExecInst;
}
+// Optimize sequence
+// %sel = V_CNDMASK_B32_e64 0, 1, %cc
+// %cmp = V_CMP_NE_U32 1, %1
+// $vcc = S_AND_B64 $exec, %cmp
+// S_CBRANCH_VCC[N]Z
+// =>
+// $vcc = S_ANDN2_B64 $exec, %cc
+// S_CBRANCH_VCC[N]Z
+//
+// It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
+// rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but
+// only 3 first instructions are really needed. S_AND_B64 with exec is a
+// required part of the pattern since V_CNDMASK_B32 writes zeroes for inactive
+// lanes.
+//
+// Returns %cc register on success.
+static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
+ const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI,
+ LiveIntervals *LIS) {
+ const SIRegisterInfo *TRI = ST.getRegisterInfo();
+ const SIInstrInfo *TII = ST.getInstrInfo();
+ const unsigned AndOpc = AMDGPU::S_AND_B64;
+ const unsigned Andn2Opc = AMDGPU::S_ANDN2_B64;
+ const unsigned CondReg = AMDGPU::VCC;
+ const unsigned ExecReg = AMDGPU::EXEC;
+
+ auto I = llvm::find_if(MBB.terminators(), [](const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
+ return Opc == AMDGPU::S_CBRANCH_VCCZ ||
+ Opc == AMDGPU::S_CBRANCH_VCCNZ; });
+ if (I == MBB.terminators().end())
+ return AMDGPU::NoRegister;
+
+ auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,
+ *I, MRI, LIS);
+ if (!And || And->getOpcode() != AndOpc ||
+ !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
+ return AMDGPU::NoRegister;
+
+ MachineOperand *AndCC = &And->getOperand(1);
+ unsigned CmpReg = AndCC->getReg();
+ unsigned CmpSubReg = AndCC->getSubReg();
+ if (CmpReg == ExecReg) {
+ AndCC = &And->getOperand(2);
+ CmpReg = AndCC->getReg();
+ CmpSubReg = AndCC->getSubReg();
+ } else if (And->getOperand(2).getReg() != ExecReg) {
+ return AMDGPU::NoRegister;
+ }
+
+ auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, MRI, LIS);
+ if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||
+ Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||
+ Cmp->getParent() != And->getParent())
+ return AMDGPU::NoRegister;
+
+ MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);
+ MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);
+ if (Op1->isImm() && Op2->isReg())
+ std::swap(Op1, Op2);
+ if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
+ return AMDGPU::NoRegister;
+
+ unsigned SelReg = Op1->getReg();
+ auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS);
+ if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
+ return AMDGPU::NoRegister;
+
+ Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);
+ Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
+ MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
+ if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
+ Op1->getImm() != 0 || Op2->getImm() != 1)
+ return AMDGPU::NoRegister;
+
+ LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t'
+ << *Cmp << '\t' << *And);
+
+ unsigned CCReg = CC->getReg();
+ LIS->RemoveMachineInstrFromMaps(*And);
+ MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
+ TII->get(Andn2Opc), And->getOperand(0).getReg())
+ .addReg(ExecReg)
+ .addReg(CCReg, CC->getSubReg());
+ And->eraseFromParent();
+ LIS->InsertMachineInstrInMaps(*Andn2);
+
+ LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
+
+ // Try to remove compare. Cmp value should not used in between of cmp
+ // and s_and_b64 if VCC or just unused if any other register.
+ if ((TargetRegisterInfo::isVirtualRegister(CmpReg) &&
+ MRI.use_nodbg_empty(CmpReg)) ||
+ (CmpReg == CondReg &&
+ std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),
+ [TRI, CondReg](const MachineInstr &MI) {
+ return MI.readsRegister(CondReg, TRI); }))) {
+ LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
+
+ LIS->RemoveMachineInstrFromMaps(*Cmp);
+ Cmp->eraseFromParent();
+
+ // Try to remove v_cndmask_b32.
+ if (TargetRegisterInfo::isVirtualRegister(SelReg) &&
+ MRI.use_nodbg_empty(SelReg)) {
+ LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
+
+ LIS->RemoveMachineInstrFromMaps(*Sel);
+ Sel->eraseFromParent();
+ }
+ }
+
+ return CCReg;
+}
+
bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
@@ -117,6 +233,14 @@
for (MachineBasicBlock &MBB : MF) {
+ if (unsigned Reg = optimizeVcndVcmpPair(MBB, ST, MRI, LIS)) {
+ RecalcRegs.insert(Reg);
+ RecalcRegs.insert(AMDGPU::VCC_LO);
+ RecalcRegs.insert(AMDGPU::VCC_HI);
+ RecalcRegs.insert(AMDGPU::SCC);
+ Changed = true;
+ }
+
// Try to remove unneeded instructions before s_endpgm.
if (MBB.succ_empty()) {
if (MBB.empty())