ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142389
diff --git a/llvm/test/MC/ARM/neont2-mul-accum-encoding.s b/llvm/test/MC/ARM/neont2-mul-accum-encoding.s
index 390ea75..34ef8c9 100644
--- a/llvm/test/MC/ARM/neont2-mul-accum-encoding.s
+++ b/llvm/test/MC/ARM/neont2-mul-accum-encoding.s
@@ -10,7 +10,7 @@
vmla.i16 q9, q8, q10
vmla.i32 q9, q8, q10
vmla.f32 q9, q8, q10
-@ vmla.i32 q12, q8, d3[0]
+ vmla.i32 q12, q8, d3[0]
@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0x42,0xef,0xa1,0x09]
@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0x52,0xef,0xa1,0x09]
@@ -20,7 +20,7 @@
@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0x50,0xef,0xe4,0x29]
@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29]
@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d]
-@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80]
+@ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80]
vmlal.s8 q8, d19, d18
@@ -63,7 +63,7 @@
vmls.i16 q9, q8, q10
vmls.i32 q9, q8, q10
vmls.f32 q9, q8, q10
-@ vmls.i16 q4, q12, d6[2]
+ vmls.i16 q4, q12, d6[2]
@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09]
@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09]
@@ -73,7 +73,7 @@
@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0x50,0xff,0xe4,0x29]
@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29]
@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d]
-@ FIXME: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x94]
+@ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x84]
vmlsl.s8 q8, d19, d18