[mips] Make isel select the correct DEXT variant up front.
Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.
Now isel selects the correct variant up front.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D16810
llvm-svn: 262229
diff --git a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
index 860bc79..511487e 100644
--- a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
+++ b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
@@ -18,7 +18,7 @@
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
; 64: mtc1 $[[OR]], $f0
-; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
+; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
; 64R2: mtc1 $[[INS]], $f0
diff --git a/llvm/test/CodeGen/Mips/fcopysign.ll b/llvm/test/CodeGen/Mips/fcopysign.ll
index 6928f2f..ffc72a1 100644
--- a/llvm/test/CodeGen/Mips/fcopysign.ll
+++ b/llvm/test/CodeGen/Mips/fcopysign.ll
@@ -27,7 +27,7 @@
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; 64: dmtc1 $[[OR]], $f0
-; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
+; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
; 64R2: dmtc1 $[[INS]], $f0
diff --git a/llvm/test/CodeGen/Mips/mips64extins.ll b/llvm/test/CodeGen/Mips/mips64extins.ll
index 211cd5f..bf68bbd 100644
--- a/llvm/test/CodeGen/Mips/mips64extins.ll
+++ b/llvm/test/CodeGen/Mips/mips64extins.ll
@@ -2,6 +2,7 @@
define i64 @dext(i64 %i) nounwind readnone {
entry:
+; CHECK-LABEL: dext:
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
%shr = lshr i64 %i, 5
%and = and i64 %shr, 1023
@@ -10,7 +11,8 @@
define i64 @dextm(i64 %i) nounwind readnone {
entry:
-; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
+; CHECK-LABEL: dextm:
+; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
%shr = lshr i64 %i, 5
%and = and i64 %shr, 17179869183
ret i64 %and
@@ -18,7 +20,8 @@
define i64 @dextu(i64 %i) nounwind readnone {
entry:
-; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
+; CHECK-LABEL: dextu:
+; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
%shr = lshr i64 %i, 34
%and = and i64 %shr, 63
ret i64 %and
@@ -26,6 +29,7 @@
define i64 @dins(i64 %i, i64 %j) nounwind readnone {
entry:
+; CHECK-LABEL: dins:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
%shl2 = shl i64 %j, 8
%and = and i64 %shl2, 261888
@@ -36,6 +40,7 @@
define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
entry:
+; CHECK-LABEL: dinsm:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
%shl4 = shl i64 %j, 10
%and = and i64 %shl4, 8796093021184
@@ -46,6 +51,7 @@
define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
entry:
+; CHECK-LABEL: dinsu:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
%shl4 = shl i64 %j, 40
%and = and i64 %shl4, 9006099743113216