| commit | 614b44bbe982dfd5930f228b3b0a5d084fd541e4 | [log] [tgz] |
|---|---|---|
| author | Amara Emerson <amara.emerson@arm.com> | Mon Nov 07 15:42:12 2016 +0000 |
| committer | Amara Emerson <amara.emerson@arm.com> | Mon Nov 07 15:42:12 2016 +0000 |
| tree | 5568cfc9ddbe5e2a41dfc7e30032f724d3bd2c22 | |
| parent | d6daac474626e3e99b730cbc0c381d46b3d4788e [diff] |
This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.
Without this patch, register allocation for the example below fails.
define half @test(half %a1, half %a2) #0 {
entry:
%0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
ret half %0
}
Patch by Florian Hahn.
Differential Revision: https://reviews.llvm.org/D25080
llvm-svn: 286111