commit 62183c4e18a964c2715cedb3f6fdc6bb3c4776bd
author Kevin Enderby <enderby@apple.com> Mon Oct 22 22:31:46 2012 +0000
committer Kevin Enderby <enderby@apple.com> Mon Oct 22 22:31:46 2012 +0000
tree 7900e3224a33ea5cc7fd9ea9e656b91d761afee4
parent 929fccd4761b3de9d6c651cc85799d4bbfd165b0

Add support for annotated disassembly output for X86 and arm.

Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm.  The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.

rdar://11764962

llvm-svn: 166445

llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp

diff --git a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
index 149be86..edad473 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
@@ -34,7 +34,11 @@
 
 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
                                      unsigned RegNo) const {
+  if (UseMarkup)
+    OS << "<reg:";
   OS << '%' << getRegisterName(RegNo);
+  if (UseMarkup)
+    OS << ">";
 }
 
 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
@@ -151,17 +155,29 @@
                                      raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
+    if (UseMarkup)
+      O << "<reg:";
     O << '%' << getRegisterName(Op.getReg());
+    if (UseMarkup)
+      O << ">";
   } else if (Op.isImm()) {
+    if (UseMarkup)
+      O << "<imm:";
     // Print X86 immediates as signed values.
     O << '$' << (int64_t)Op.getImm();
+    if (UseMarkup)
+      O << ">";
     
     if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
       *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
     
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
+    if (UseMarkup)
+      O << "<imm:";
     O << '$' << *Op.getExpr();
+    if (UseMarkup)
+      O << ">";
   }
 }
 
@@ -172,6 +188,9 @@
   const MCOperand &DispSpec = MI->getOperand(Op+3);
   const MCOperand &SegReg = MI->getOperand(Op+4);
   
+  if (UseMarkup)
+    O << "<mem:";
+
   // If this has a segment register, print it.
   if (SegReg.getReg()) {
     printOperand(MI, Op+4, O);
@@ -196,9 +215,18 @@
       O << ',';
       printOperand(MI, Op+2, O);
       unsigned ScaleVal = MI->getOperand(Op+1).getImm();
-      if (ScaleVal != 1)
-        O << ',' << ScaleVal;
+      if (ScaleVal != 1) {
+        O << ',';
+        if (UseMarkup)
+          O << "<imm:";
+        O << ScaleVal;
+        if (UseMarkup)
+          O << ">";
+      }
     }
     O << ')';
   }
+
+  if (UseMarkup)
+    O << ">";
 }