commit 6221be8e461ef5ce6cba05904260f697ce09eb81
author Zlatko Buljan <Zlatko.Buljan@imgtec.com> Thu Mar 31 08:51:24 2016 +0000
committer Zlatko Buljan <Zlatko.Buljan@imgtec.com> Thu Mar 31 08:51:24 2016 +0000
tree 886a17f868eab556c6f6faf4c73a2e8a730a0748
parent 52aadc8eb869ee5327b98fcff0d8d28d1d7c8dc1

[mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 8f7aeb2..81c1868 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -44,6 +44,7 @@
   bool hasMips32r6() const {
     return STI.getFeatureBits()[Mips::FeatureMips32r6];
   }
+  bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
 
   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
 
@@ -919,9 +920,9 @@
       return Result;
     }
 
-    if (hasMips32r6()) {
-      DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n");
-      Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn,
+    if (hasMips32r6() && isFP64()) {
+      DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
+      Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn,
                                  Address, this, STI);
       if (Result != MCDisassembler::Fail) {
         Size = 4;