[mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132
This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132.
It also includes patterns for instruction selection and test cases.
Reviewed by D. Sanders
llvm-svn: 226573
diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll
index 9d82b74..f7fbfb1 100644
--- a/llvm/test/CodeGen/Mips/octeon.ll
+++ b/llvm/test/CodeGen/Mips/octeon.ll
@@ -93,3 +93,75 @@
%res2 = zext i1 %res to i64
ret i64 %res2
}
+
+define i64 @bbit0(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: bbit0:
+; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64-LABEL: bbit0:
+; MIPS64: andi $[[T0:[0-9]+]], $4, 8
+; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
+ %bit = and i64 %a, 8
+ %res = icmp eq i64 %bit, 0
+ br i1 %res, label %endif, label %if
+if:
+ ret i64 48
+
+endif:
+ ret i64 12
+}
+
+define i64 @bbit032(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: bbit032:
+; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64-LABEL: bbit032:
+; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
+; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
+; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
+; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
+ %bit = and i64 %a, 34359738368
+ %res = icmp eq i64 %bit, 0
+ br i1 %res, label %endif, label %if
+if:
+ ret i64 48
+
+endif:
+ ret i64 12
+}
+
+define i64 @bbit1(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: bbit1:
+; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64-LABEL: bbit1:
+; MIPS64: andi $[[T0:[0-9]+]], $4, 8
+; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
+ %bit = and i64 %a, 8
+ %res = icmp ne i64 %bit, 0
+ br i1 %res, label %endif, label %if
+if:
+ ret i64 48
+
+endif:
+ ret i64 12
+}
+
+define i64 @bbit132(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: bbit132:
+; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
+; MIPS64-LABEL: bbit132:
+; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
+; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
+; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
+; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
+ %bit = and i64 %a, 34359738368
+ %res = icmp ne i64 %bit, 0
+ br i1 %res, label %endif, label %if
+if:
+ ret i64 48
+
+endif:
+ ret i64 12
+}
diff --git a/llvm/test/MC/Mips/octeon-instructions.s b/llvm/test/MC/Mips/octeon-instructions.s
index 2922744..e98bbe4 100644
--- a/llvm/test/MC/Mips/octeon-instructions.s
+++ b/llvm/test/MC/Mips/octeon-instructions.s
@@ -3,6 +3,10 @@
# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28]
+# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A]
+# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A]
+# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A]
+# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A]
# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2]
# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72]
# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3]
@@ -46,9 +50,14 @@
# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f]
# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f]
+foo:
baddu $9, $6, $7
baddu $17, $18, $19
baddu $2, $3
+ bbit0 $19, 22, foo
+ bbit032 $30, 11, foo
+ bbit1 $3, 31, foo
+ bbit132 $24, 10, foo
cins $25, $10, 22, 2
cins $9, 17, 29
cins32 $15, $2, 18, 8