| commit | 8adb9944aafd95a15264f27fc02eeecbde1d1d94 | [log] [tgz] |
|---|---|---|
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:02:22 2003 +0000 |
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | Tue May 27 00:02:22 2003 +0000 |
| tree | 34462566d8a9913c788234ee1d688579046149fd | |
| parent | 196897c42457211b000ca17e9e90f5cee75ba2a5 [diff] |
Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339